The Automated Lint Error Rectifier Tool (ALERT) addresses a major productivity bottleneck in the global semiconductor industry. As designs move towards sub-5nm nodes, manually resolving Hardware Description Language (HDL) lint errors is increasingly unscalable, contributing to costly delays and silicon respins that can reach €25 million. While existing EDA tools provide sophisticated error diagnostics, they do not automate the remediation process.
ALERT bridges this identification–resolution gap using Attribute-Enhanced Grammatical Evolution (GE), a machine-learning approach that automatically generates semantically correct, synthesis-ready HDL while maintaining functional equivalence and minimising regressions. By automating routine lint remediation, ALERT aims to reduce designer effort and accelerate design closure.
With 70–80% of the foundational technical work already completed (TRL 3/4), the 24-month project will focus on industrial hardening, scaling, and validation to reach TRL 7. Led by a team combining expertise from the inventor of GE and semiconductor industry specialists, and supported by the Lero and ARC Hub ecosystems, the project will target an 80% reduction in lint-closure time.
The project will establish the technical and commercial basis for deployment through a spin-out or licensing to Tier-1 EDA vendors, strengthening Ireland’s position in semiconductor design automation and supporting its €13 billion semiconductor export sector.
